\section{Current Integrator}
\label{sec:CurrentIntegrator}

\subsection{Design}

The Current Integrator uses a Simple Transconductance Amplifier (Listing ~\ref{lst:STA}) with $G_m = 250nS$ and $R_{out}=1G\Ohm$. The schematic is shown on Figure~\ref{fig:CI_schematic}. 

\begin{figure}[H]
\begin{center}
\begin{tabular}{c}
	\includegraphics[height=2.5in]{../Data/CurrentIntegrator_NFETswitch_schematic.png} \\
	(a) nFET Switch \\
	\includegraphics[height=2.5in]{../Data/CurrentIntegrator_TGATEswitch_schematic.png} \\
	(b) T-gate Switch \\	
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{ Schematic for a Current Integrator.}
\label{fig:CI_schematic}
\end{figure}

\subsection{Evaluation}
\subsubsection{Integration slopes and Miller capacitance}
Theoretically, 
\[\frac{dV_s}{dt}=\frac{1}{1-A}\frac{I_s}{C}\]
\[\frac{dV_out}{dt}=\frac{A}{1-A}\frac{I_s}{C}\]
The relationship of the two integration slopes
\[\frac{dV_out}{dt}=A\frac{dV_s}{dt}\]
In our case, 
\[A=g_m R_out=250\]
\[C_{Miller}=(1-A)C=2.49nF\]

The results of 1s transient simulation are shown on Figure~\ref{fig:CI_Sims} (a) and (b).
The ratio of the integration slopes are \(\frac{932.72}{3.728}=250.19\) and \(\frac{1382.3}{5.4932}=251.6\). They match the theoretical values. 
The Miller capacitance are \(\frac{10 \times 10^{-12}}{3.804 \times 10^{-3}}=2.628n\) and \(\frac{15 \times 10^{-12}}{5.7094 \times 10^{-3}}=2.627n\). They also match the theoretical values.
Compare Figure~\ref{fig:CI_Sims} (a) and (b), as increased \(I_s\), the absolute value of the integration slopes increased. It matches the formula.

\begin{figure}[H]
\begin{center}
\begin{tabular}{c}
	\includegraphics[width=3.25in]{../Data/CurrentIntegrator_NFETswitch_10pA.png} \\
	\includegraphics[width=3.25in]{../Data/CurrentIntegrator_NFETswitch_15pA.png} \\
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{Results for transient simulation of the Current Integrator with changing \(I_s\). (a) \(I_s=10pF\) (b) \(I_s=15pF\)}
\label{fig:CI_Sims}
\end{figure}


By increasing the simulation time to 5s, we can see current integrator failed when the \(V_out\) is clipping, as shown on Figure~\ref{fig:CI_saturated}.

\begin{figure}[H] \centering
\includegraphics[width=\columnwidth]{../Data/CurrentIntegrator_saturated.png}
\caption{\label{fig:CI_saturated} Failed case when saturated}
\end{figure}

\subsubsection{T-gates}
The simulation result of circuit with T-gate is shown on Figure~\ref{fig:CI_tgate}. As the feed-through error is caused by both PFET and NFET, we can see the feed-through error in two different direction.

\begin{figure}[H] \centering
\includegraphics[width=\columnwidth]{../Data/CurrentIntegrator_Tgate.png}
\caption{\label{fig:CI_tgate} Results for transient simulation of the Current Integrator with T-gate}
\end{figure}


\subsubsection{Adjust reference voltage}
The simulation results are shown on Figure~\ref{fig:CI_refVoltage} (a) and (b). As \(V_ref\) sweep from 0V to 5V, the feed-through error first increased and then decreased. The max error is in the point when \(V_ref\) about 2V.

\begin{figure}[H] \centering
\includegraphics[height=1.5in]{../Data/CurrentIntegrator_NFETswitch_10pA_feedthru.png}
\caption{\label{fig:CI_refVoltage} Results for transient simulation of the Current Integrator with changing reference voltage.}
\end{figure}

